1. Technical Field
The present invention relates to logic-based processing device testings in general, and in particular to an apparatus for detecting bugs in logic-based processing devices.
2. Description of Related Art The manufacturing process of logic-based processing devices typically includes several stages such as design, verification, validation and production stages. Initially, the logic circuit of a logic-based processing device is designed by using various software design tools. Before any physical devices are made, the functionalities of the logic circuit design are verified (i.e., pre-silicon verification) to allow circuit designers to locate and fix any bugs in the logic circuit design. If the logic circuit design passes the pre-silicon verification, a limited number of physical prototype devices are made, and tests are then performed on the physical prototype devices post-silicon validation) to detect any bugs attributable not only to the architecture of the logic circuit design, but also due to process variations, manufacturing defects, and environmental variations. After all the detected bugs have been fixed, the logic-based processing device can then be sent to large-scale production.
During pre-silicon verification, a virtualized logic-based processing device is loaded into a verification system such as a simulator or emulator. After providing input data to the virtualized logic-based processing device, the verification system then performs a battery of tests on the behavior of the virtualized logic-based processing device. If the behavior of the virtualized logic-based processing device differs from what is expected from the given input data, it means there is a bug in the logic circuit design.
Post-silicon validation is similar to pre-silicon verification, but occurs on the physical prototype devices. Post-silicon validation is essentially the real world counterpart of the pre-silicon verification. Conventional approaches to post-silicon validation suffer from the same error detection latency problems as those in pre-silicon verification; that is, it may take several billion clock cycles between the occurrence of an error and the detection thereof.
Consequently, it would be desirable to provide an improved apparatus for performing post-silicon validation with a shorter error detection latency.